External compensation for a display device using varying gate pulse timing

ABSTRACT

A display device comprises a display panel and a timing controller. The timing controller supplies gate timing signals to a gate driver as a sequence of clock pulses that sequentially select different ones of the display lines for receiving the data signals during the vertical active periods and for receiving a sensing signal during the vertical blanking intervals. The clock pulses have a first timing during the vertical active periods and the clock pulses have a second timing during the vertical blanking intervals in which the second timing is different than the first timing.

This application claims the benefit of Korea Patent Application No. 10-2016-0160276 filed on Nov. 29, 2016, which is incorporated herein by reference for all purposes as if fully set forth herein.

BACKGROUND Technical Field

The present disclosure relates to external compensation for a display device and a method of driving the same.

Discussion of the Related Art

Various types of panel displays have been developed and sold. Among the various types of flat panel displays, an electroluminescent display is classified into an inorganic electroluminescent display and an organic electroluminescent display depending on a material of an emission layer. In particular, an active matrix organic light emitting diode (OLED) display includes a plurality of OLEDs capable of emitting light by themselves and has many advantages, such as fast response time, high emission efficiency, high luminance, wide viewing angle, and the like.

An OLED serving as a self-emitting element includes an anode electrode, a cathode electrode, and an organic compound layer between the anode electrode and the cathode electrode. The organic compound layer includes a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL. When a power voltage is applied to the anode electrode and the cathode electrode, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the emission layer EML and form excitons. As a result, the emission layer EML generates visible light.

An OLED display includes a plurality of pixels, each including an OLED and a thin film transistor (TFT) that adjusts a luminance of an image implemented on the pixels based on a grayscale of image data. The driving TFT controls a driving current flowing in the OLED depending on a voltage (hereinafter, referred to as “a gate-to-source voltage”) between a gate electrode and a source electrode of the driving TFT. An amount of light emitted by the OLED is determined depending on the driving current of the OLED, and the luminance of the image is determined depending on the amount of light emitted by the OLED.

In general, when a driving TFT operates in a saturation region, a pixel current Ids flowing between a drain electrode and a source electrode of the driving TFT is expressed by the following Equation 1. [Equation 1] Ids=½*(μ*C*W/L)*(Vgs−Vth)²

In the above Equation 1, μ is electron mobility, C is a capacitance of a gate insulating layer, W is a channel width of the driving TFT, and L is a channel length of the driving TFT. In addition, Vgs is a voltage between a gate electrode and a source electrode of the driving TFT, and Vth is a threshold voltage (or a critical voltage) of the driving TFT. A gate-to-source voltage Vgs of the driving TFT may be a voltage differential between a data voltage and a reference voltage in accordance with a pixel structure. The data voltage is an analog voltage corresponding to a grayscale of image data, and the reference voltage is a fixed voltage. Therefore, the gate-to-source voltage Vgs of the driving TFT is programmed or set depending on the data voltage. Then, the pixel current Ids is determined depending on the programmed gate-to-source voltage Vgs.

Electrical characteristics of the pixel, such as the threshold voltage Vth and the electron mobility μ of the driving TFT and a threshold voltage of the OLED, may be factors determining an amount of pixel current Ids of the driving TFT. Therefore, all the pixels should have the same electrical characteristics. However, a variation in the electrical characteristics between the pixels may be caused by various factors such as manufacturing process characteristics and time-varying characteristics. The variation in the electrical characteristics between the pixels may lead to a luminance variation, and it is difficult to implement desired images or meet image quality requirements.

In order to compensate for the luminance variation between the pixels, there are so-called external compensation techniques for sensing electrical characteristics of the pixels and correcting (or compensating for) tan input image based on the sensing result. In order to compensate for the luminance variation, a current change by an amount of Δy has to be ensured when the data voltage applied to the pixel is changed by an amount of “Δx”. Thus, the external compensation technique is to implement the same (or effectively the same) brightness by calculating “Δx” for each pixel and applying the same pixel current to the OLED. Namely, the external compensation technique may be implemented to adjust gray levels so that the pixels have the same brightness.

The electrical characteristics of the pixels may continuously change during the driving of the pixels. Thus, a real-time compensation technique for compensating for changes in the electrical characteristics of each pixel in real time may be needed to increase an external compensation performance.

In order to implement such real-time compensation techniques, a method has been proposed to perform a sensing drive operation in a vertical blanking interval, in which input image data is not written. The vertical blanking interval is disposed between every adjacent vertical active period in which input image data is written in one frame. A related art driving circuit for external compensation senses one display line in a vertical blanking interval of each frame period. To this end, a gate driver included in the related art driving circuit for external compensation generates a sensing gate signal during the vertical blanking interval and applies the sensing gate signal to pixels formed on a sensing target display line. The gate driver includes a plurality of cascade-connected stages.

A length of the vertical blanking interval is much shorter than a length of the vertical active period. Because each of the stages constituting the gate driver receives an output signal of a previous stage as a carry signal and sequentially operates in response to the carry signal, limited time of the vertical blanking interval may be insufficient to generate a desired sensing gate signal. For example, an Nth sensing gate signal generated in an Nth stage is necessary to sense an Nth display line of a display panel having a vertical resolution of “N”. However, because the Nth stage is driven after all of the first to (N−1)th stages are sequentially driven, all of the N stages included in the gate driver have to be driven to generate the Nth sensing gate signal. However, one vertical blanking interval does not provide enough time to operate all the stages of the gate driver. Such a problem is magnified and becomes more significant as the vertical resolution of the display panel increases and as the number of display lines to be sensed in one vertical blanking interval increases.

SUMMARY

The present disclosure provides external compensation for a display device and a method of driving the same capable of generating a desired sensing gate signal without time constraints by extending a vertical blanking interval and performing a sensing drive in an extended vertical blanking interval.

In one aspect, a display device comprises a display panel and a timing controller. The display panel includes a plurality of pixels arranged in display lines, a plurality of display gate lines, and a plurality of data lines. The display lines are driven with the data signals from the data lines according to timing of gate pulses from the display gate lines to display image data during vertical active periods. The timing controller supplies gate timing signals to a gate driver as a sequence of clock pulses that sequentially select different ones of the display lines for receiving the data signals during the vertical active periods and for selecting a sensing target display line for receiving a sensing signal during the vertical blanking intervals. The clock pulses have a first timing during the vertical active periods and the clock pulses have a second timing during the vertical blanking intervals in which the second timing is different than the first timing.

In another aspect, a display device comprises a display panel and a timing controller. The display panel includes a plurality of pixels arranged in display lines, a plurality of gate lines, and a plurality of data lines. The display lines are driven with data signals from the data lines according to timing of gate pulses from the display gate lines to display image data during vertical active periods. The vertical blanking intervals include normal vertical blanking intervals and extended vertical blanking intervals longer than the normal vertical blanking intervals. The vertical active periods include normal vertical active periods and shortened vertical active periods shorter than the normal vertical active periods. The timing controller supplies timing signals to a gate driver as a sequence of gate pulses to cause the gate driver to sequentially select different ones of the display lines for receiving the data signals during the vertical active periods and to select a sensing target display line for sensing of the electrical characteristics during the extended vertical blanking intervals.

In another aspect, a controller controls a display panel having a plurality of pixels arranged in display lines, a plurality of gate lines, and a plurality of data lines. The controller comprises a timing controller and a sensing circuit. The timing controller controls timing of vertical active periods and vertical blanking intervals in between the vertical active periods. During the vertical active periods, the timing controller supplies first timing signals to a gate driver as a first sequence of clock pulses that causes the gate driver to sequentially provide first gate pulses on the plurality of display gate lines to select different display lines for receiving data signals to display image data. During the vertical blanking intervals, the timing controller supplies second gate timing signals to the gate driver as a second sequence of clock pulses that causes the gate driver to select a sensing target display line for sensing. The first clock pulses during the vertical active periods have a first timing and the second clock pulses during the vertical blanking intervals have a second timing different than the first timing. The sensing circuit receives the electrical characteristics of the sensing target display lines during the vertical blanking intervals.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 is a block diagram of an electroluminescent display for external compensation according to an embodiment of the invention;

FIG. 2 schematically illustrates a connection configuration between a driving circuit for external compensation according to an embodiment of the invention and a pixel;

FIG. 3 illustrates another connection configuration between a driving circuit for external compensation according to an embodiment of the invention and a pixel;

FIG. 4 is a flow chart illustrating an external compensation method according to an embodiment of the invention;

FIG. 5A illustrates that a reference curve equation is obtained in an external compensation method of FIG. 4;

FIG. 5B illustrates an average I-V curve of a display panel and an I-V curve of a pixel to be compensated in an external compensation method of FIG. 4;

FIG. 5C illustrates an average I-V curve of a display panel, an I-V curve of a pixel to be compensated, and an I-V curve of a compensated pixel in an external compensation method of FIG. 4;

FIGS. 6 to 8 illustrate various examples of an external compensation module;

FIG. 9 illustrates an example of a pixel array included in a display panel;

FIG. 10 illustrates another example of a pixel array included in a display panel;

FIG. 11 is an equivalent circuit diagram of a pixel included in a pixel array of FIGS. 9 and 10;

FIG. 12 illustrates an exemplary configuration of a gate driver for driving a pixel array of FIG. 9;

FIG. 13 illustrates an exemplary configuration of a gate driver for driving a pixel array of FIG. 10;

FIGS. 14 and 15 schematically illustrate an external compensation technique according to an embodiment of the invention in which a real-time sensing drive is performed in an extended vertical blanking interval;

FIGS. 16A to 16C illustrate operation examples of a gate driver in a vertical blanking interval extended corresponding to a display line, on which a real-time sensing drive is performed;

FIG. 17 illustrates an example of modifying a gate timing control signal to be input to a gate driver of FIG. 12 in order to secure a sensing time when a k-th display line is sensed in an extended vertical blanking interval; and

FIG. 18 illustrates an example of modifying a gate timing control signal to be input to a gate driver of FIG. 13 in order to secure a sensing time when a k-th display line is sensed in an extended vertical blanking interval.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. However, the present disclosure is not limited to embodiments disclosed below, and may be implemented in various forms. These embodiments are provided so that the present disclosure will be described more completely, and will fully convey the scope of the present disclosure to those skilled in the art to which the present disclosure pertains. Particular features of the present disclosure can be defined by the scope of the claims.

Shapes, sizes, ratios, angles, number, and the like illustrated in the drawings for describing embodiments of the present disclosure are merely exemplary, and the present disclosure is not limited thereto unless specified as such. Like reference numerals designate like elements throughout. In the following description, when a detailed description of certain functions or configurations related to this document that may unnecessarily cloud the gist of the invention have been omitted.

In the present disclosure, when the terms “include”, “have”, “comprised of”, etc. are used, other components may be added unless “˜only” is used. A singular expression can include a plural expression as long as it does not have an apparently different meaning in context.

In the explanation of components, even if there is no separate description, it is interpreted as including margins of error or an error range.

In the description of positional relationships, when a structure is described as being positioned “on or above”, “under or below”, “next to” another structure, this description should be construed as including a case in which the structures directly contact each other as well as a case in which a third structure is disposed therebetween.

The terms “first”, “second”, etc. may be used to describe various components, but the components are not limited by such terms. The terms are used only for the purpose of distinguishing one component from other components. For example, a first component may be designated as a second component, and vice versa, without departing from the scope of the present invention.

The features of various embodiments of the present disclosure can be partially combined or entirely combined with each other, and can be technically interlocking-driven in various ways. The embodiments can be independently implemented, or can be implemented in conjunction with each other.

Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the following embodiments, an electroluminescent display will be described focusing on an organic light emitting diode (OLED) display including an organic light emitting material. However, it should be noted that embodiments of the present disclosure are not limited to the OLED display, and may be applied to an inorganic light emitting display including an inorganic light emitting material. Further, it should be noted that embodiments of the present disclosure may be applied not only to an electroluminescent display but also to various display devices such as a flexible display device and a wearable display device.

FIG. 1 is a block diagram of an electroluminescent display for external compensation according to an embodiment of the invention. FIGS. 2 and 3 illustrate connection configurations between a driving circuit for real-time external compensation according to an embodiment of the invention and a pixel. FIG. 4 is a flow chart illustrating an external compensation method according to an embodiment of the invention. FIG. 5A illustrates that a reference curve equation is obtained in the external compensation method of FIG. 4. FIG. 5B illustrates an average I-V curve of a display panel and an I-V curve of a pixel to be compensated in the external compensation method of FIG. 4. FIG. 5C illustrates an average I-V curve of a display panel, an I-V curve of a pixel to be compensated, and an I-V curve of a compensated pixel in the external compensation method of FIG. 4.

Referring to FIGS. 1 to 3, an electroluminescent display according to an embodiment of the invention may include a display panel 10, a driver IC (or referred to as “D-IC”) 20, a compensation IC 30, a host system 40, and a storage memory 50. A driving circuit for real-time external compensation according to the embodiment of the invention includes a gate driver 15 included in the display panel 10, the driver IC 20, the compensation IC 30, and the storage memory 50.

The display panel 10 includes a plurality of pixels P arranged in display lines and a plurality of signal lines. The signal lines may include data lines 140 for supplying data signals (e.g., an analog data voltage Vdata) to the pixels P and gate lines 160 for supplying a gate signal to the pixels P. To display image data, the display lines are driven with the data signals from the data lines according to timing of gate pulses from display gate lines, as will be described in further detail below. Particularly, image data is displayed during the vertical active periods. In an embodiment, the gate pulses are not provided to display gate lines (used to select pixels to receive data for display) other than a sensing target line during the vertical blanking intervals. In one embodiment, the data signals for displaying image data are not provided to the display lines during the vertical blanking intervals. In the embodiments disclosed herein, the gate signal may include a first gate signal and a second gate signal. In this instance, each gate line 160 may include a first gate line for supplying the first gate signal and a second gate line for supplying the second gate signal. The signal lines may further include sensing lines 150 that are used to sense electrical characteristics of the pixels P. However, the sensing lines 150 may be omitted depending on a circuit configuration of the pixels P. In this instance, the electrical characteristics of the pixels P may be sensed through the data lines 140.

The pixels P of the display panel 10 are disposed in a matrix to form a pixel array. Each pixel P may be connected to one of the data lines 140, one of the sensing lines 150, and at least one of the gate lines 160. Each pixel P is configured to receive a high potential pixel power and a low potential pixel power from a power source or generator. To this end, the power generator may supply the high potential pixel power to the pixel P through a high potential pixel power line or a pad and may supply the low potential pixel power to the pixel P through a low potential pixel power line or a pad.

The driver IC 20 may include a timing controller 21 and a data driver 25. The data driver 25 may include a sensor 22 and a data voltage generator 23. However, the embodiments are not limited thereto.

The timing controller 21 may generate a gate timing control signal GDC for controlling operation timing of the gate driver 15 and a data timing control signal DDC for controlling operation timing of the data driver 25 based on timing signals, for example, a vertical sync signal Vsync, a horizontal sync signal Hsync, a dot clock signal DCLK, and a data enable signal DE received from the host system 40.

The data timing control signal DDC may include a source start pulse, a source sampling clock, and a source output enable signal, and the like, but is not limited thereto. The source start pulse controls start timing of data sampling of the data voltage generator 23. The source sampling clock is a clock signal that controls the sampling timing of data based on a rising edge or a falling edge thereof. The source output enable signal controls output timing of the data voltage generator 23.

The gate timing control signal GDC may include a gate start pulse, a gate shift clock, and the like, but is not limited thereto. The gate start pulse is applied to a stage of the gate driver 15 for generating a first output and activates an operation of the stage. The gate shift clock is a clock signal that is commonly input to stages and shifts the gate start pulse.

The timing controller 21 controls a sensing drive timing of one display line (or display lines) of the display panel 10 and a display drive timing of other display lines of the display panel 10 in accordance with a particular sequence, thereby implementing real-time sensing. In embodiments disclosed herein, the “display line” indicates not a physical signal line but a pixel block line formed by the adjacent pixels P. In the following description, the display line, on which the sensing drive is performed, is referred to as a “sensing target display line”.

The sensing drive operation is an operation of sensing electrical characteristics of corresponding pixels P disposed on a sensing target display line, converting a sensing result (i.e., an analog sensing voltage Vsen) of the corresponding pixels P into digital sensing data S-DATA, and updating a compensation value for compensating for changes in the electrical characteristics of the corresponding pixels P based on the digital sensing data S-DATA. The display drive operation is an operation of writing input image data to display lines and displaying an input image on the display lines. Namely, the display drive operation is an operation of displaying the input image on previously sensed display lines. The display drive operation modulates digital image data to be input to the previously sensed pixels P based on the updated compensation value and applies an analog data voltage Vdata corresponding to modulated digital image data V-DATA to the corresponding pixels P, thereby displaying the input image on the previously sensed pixels.

The display drive operation is performed in a vertical active period of each frame, and the sensing drive is performed in a vertical blanking interval of each frame. During the vertical active periods, the gate timing control signal GDC comprises clock pulses that control the gate driver 15 to supply the gate pulses to the gate lines to sequentially select different ones of the display lines for receiving the data signals for display. During the extended vertical blanking intervals, the clock pulses may furthermore cause the gate driver 15 to select a sensing target display line for sensing of the electrical characteristics from the sensing target display line. The timing controller 21 shortens a length of a vertical active period for the display drive in one frame, extends a vertical blanking interval by an amount equal to the shortened length of the vertical active period, and performs the sensing drive operation during the extended vertical blanking interval, in order to secure a sufficient sensing time in the one frame.

The timing controller 21 may differently generate timing control signals GDC and DDC for the display drive operation and timing control signals GDC and DDC for the sensing drive operation. The timing controller 21 outputs a first gate timing control signal for display-driving the plurality of display lines during the shortened vertical active period and outputs a second gate timing control signal for sensing-driving a sensing target display line of the plurality of display lines during the extended vertical blanking interval. In this instance, the timing controller 21 may cause a clock cycle of the first gate timing control signal to be different from a clock cycle of the second gate timing control signal, in order to secure a more sufficient sensing time. Thus, the timing control signal includes clock pulses that have a first timing (e.g., a first pulse width and first frequency) during the shortened vertical active period and have a second timing (e.g., a second pulse width and second frequency) during the extended vertical blanking intervals in which the second timing is different than the first timing. This is described in detail below with reference to FIGS. 14 to 18.

The data voltage generator 23 includes a digital-to-analog converter (DAC) converting a digital signal into an analog signal. The data voltage generator 23 generates a display data voltage Vdata-DIS for the display drive operation and applies the display data voltage Vdata-DIS to the previously sensed pixels P of the display panel 10. To this end, the data voltage generator 23 may convert digital image data V-DATA modulated by the compensation IC 30 into an analog gamma voltage and output a conversion result to the data lines 140 as the display data voltage Vdata-DIS. Further, the data voltage generator 23 generates a sensing data voltage Vdata-SEN for the sensing drive and applies the sensing data voltage Vdata-SEN to the sensing target pixels P of the display panel 10 through the data lines 140.

In order to perform the sensing drive operation, the sensor 22 may sense electrical characteristics of the sensing target pixels P, for example, electrical characteristics of driving elements and/or light emitting elements included in the sensing target pixels P through the sensing lines 150. The sensor 22 may include a voltage sensing unit or a current sensing unit. The voltage sensing unit may sense a voltage charged to a specific node of the sensing target pixel P as an analog sensing voltage Vsen. The current sensing unit may directly sense a current flowing in a specific node of the sensing target pixel P and obtain an analog sensing voltage Vsen.

As shown in FIG. 2, the voltage sensing unit includes a sample and hold circuit SH, an analog-to-digital converter (ADC), and first and second switches SW1 and SW2. The voltage sensing unit senses a voltage of a source electrode of a driving element included in the sensing target pixel P (i.e., a current of the driving element charged to a line capacitor of the sensing line 150), that depends on a pixel current of the driving element. The first and second switches SW1 and SW2 are selectively turned on. The first switch SW1 is a switch for supplying an initialization voltage Vpre to the sensing line 150, and the second switch SW2 is a switch that is turned on in synchronization with sampling timing of the analog sensing voltage Vsen. The sample and hold circuit SH is connected to the sensing line 150 during the turn-on of the second switch SW2 and senses a voltage charged to the line capacitor of the sensing line 150 as the analog sensing voltage Vsen. The ADC converts the analog sensing voltage Vsen sampled by the sample and hold circuit SH into digital sensing data S-DATA.

As shown in FIG. 3, the current sensing unit further includes a current integrator at a previous stage of a sample and hold circuit SH and directly senses the pixel current of the driving element included in the sensing target pixel P flowing in the sensing line 150. The current integrator integrates the pixel current flowing through the sensing line 150 and generates the analog sensing voltage Vsen. The current integrator includes an amplifier AMP including an inverting input terminal (−) receiving the pixel current of the driving element from the sensing line 150, a non-inverting input terminal (+) receiving the initialization voltage Vpre, and an output terminal, an integrating capacitor Cfb connected between the inverting input terminal (−) and the output terminal of the amplifier AMP, and a reset switch RST connected to both ends of the integrating capacitor Cfb. The current integrator is connected to the ADC via the sample and hold circuit SH. The sample and hold circuit SH samples the analog sensing voltage Vsen output from the amplifier AMP and supplies the sampled analog sensing voltage Vsen to the ADC. The ADC converts analog sensing values Vsen sampled by the sample and hold circuit SH into digital sensing data S-DATA.

The sensor 22 may simultaneously process a plurality of analog sensing values Vsen using a plurality of ADCs in parallel and may sequentially process the plurality of analog sensing values Vsen using one ADC in series. A sampling rate of the ADC and the accuracy of the sensing are in a trade-off relationship. The ADC using a parallel processing method is advantageous to increase the accuracy of the sensing because the ADC using the parallel processing method can further reduce a sampling rate compared to the ADC using a serial processing method. The ADC may be implemented as a flash ADC, an ADC using a tracking method, a successive approximation register ADC, and the like. In the sensing drive, the ADC converts the analog sensing voltage Vsen into the digital sensing data S-DATA and then supplies the digital sensing data S-DATA to the storage memory 50.

In the sensing drive operation, the storage memory 50 stores the digital sensing data S-DATA input from the sensor 22. The storage memory 50 may be implemented as a flash memory, but is not limited thereto.

In order to perform the display drive operation, the compensation IC 30 calculates an offset and a gain for each pixel based on the digital sensing data S-DATA read from the storage memory 50. The compensation IC 30 modulates (or corrects) digital image data to be input to the previously sensed pixels P depending on the calculated offset and gain, and supplies the modulated digital image data V-DATA to the driver IC 20. To this end, the compensation IC 30 may include a compensator 31 and a compensation memory 32.

The compensation memory 32 allows access to the digital sensing data S-DATA read from the storage memory 50 to the compensator 31. The compensation memory 32 may be a random access memory (RAM), for example, a double data rate synchronous dynamic RAM (DDR SDRAM), but is not limited thereto.

As shown in FIGS. 4 to 5C, the compensator 31 may include a compensation algorithm that performs a compensation operation so that a current (I)-voltage (V) curve of a pixel to be compensated coincides with an average I-V curve. The average I-V curve may be obtained through a plurality of sensing operations.

More specifically, as shown in FIGS. 4 and 5A, the compensator 31 performs the sensing of a plurality of gray levels (for example, a total of seven gray levels A to G) and then obtains the following Equation 2 corresponding to the average I-V curve through a known least square method in step S1. [Equation 2] I=a(V _(data) −b)^(c)

where “a” is electron mobility of the driving TFT, “b” is a threshold voltage of the driving TFT, and “c” is a physical property value of the driving TFT.

As shown in FIGS. 4 and 5B, the compensator 31 calculates parameter values a′ and b′ of the previously sensed pixel P based on current values I1 and I2 and gray values (gray levels X and Y) (i.e., data voltage values Vdata1 and Vdata2 of digital level) measured at two points in step S2. [Equation 3] I ₁ =a′(V _(data1) −b′)^(c) I ₂ =a′(V _(data2) −b′)^(c)

The compensator 31 may calculate the parameter values a′ and b′ of the previously sensed pixel P using a quadratic equation in the above Equation 3.

As shown in FIGS. 4 and 5C, the compensator 31 may calculate an offset and a gain for causing the I-V curve of the pixel to be compensated to coincide with the average I-V curve in step S3. The offset and the gain of the compensated pixel are expressed by Equation 4. [Equation 4] V _(comp)=(a/a′)^(1/c) ×V _(data)+(b′−b(a/a′)^(1/c))

where “Vcomp” is a compensation voltage, (a/a′)^(1/c) is the gain, and (b′−b(a/a′)^(1/c)) is the offset.

The compensator 31 corrects digital image data to be input to the previously sensed pixel P so that the digital image data corresponds to the compensation voltage Vcomp, in step S4. In other words, the compensator 31 converts digital image data to be input to the previously sensed pixel P into a data voltage value Vdata of a digital level. The compensator 31 multiplies the gain by the data voltage value Vdata and then adds the offset to it, thereby generating the compensation voltage Vcomp of the digital level. The compensator 31 converts the compensation voltage Vcomp of the digital level into the modulated digital image data V-DATA.

The host system 40 may supply digital image data to be input to the pixels P of the display panel 10 to the compensation IC 30. The host system 40 may further supply user input information, for example, digital brightness information to the compensation IC 30. The host system 40 may be implemented as an application processor.

The gate driver 15 generates a display gate signal for the display drive based on the gate timing control signal GDC and supplies the display gate signal to the gate lines 160 connected to the display lines. The display gate signal is a signal synchronized with an application timing of the display data voltage Vdata-DIS. The gate driver 15 generates a sensing gate signal for the sensing drive based on the gate timing control signal GDC and supplies the sensing gate signal to the gate lines 160 connected to the sensing target display line. The sensing gate signal is a signal synchronized with an application timing of the sensing data voltage Vdata-SEN.

The gate driver 15 includes a gate shift register that operates in response to the gate timing control signal GDC received from a level shifter. The level shifter may be included in the timing controller 21, but is not limited thereto. The level shifter may receive the gate timing control signal GDC including the gate start pulse and N-phase gate shift clocks from the timing controller 21, where N is an integer equal to or greater than 2. The level shifter level-shifts a transistor-transistor-logic (TTL) level voltage of the gate timing control signal GDC to a gate high voltage and a gate low voltage that can switch on and off a TFT of the gate shift register. The level shifter supplies the level-shifted gate start pulse and the level-shifted N-phase gate shift clocks to the gate shift register.

The gate shift register includes a plurality of stages, each of which shifts the gate start pulse in response to the N-phase gate shift clocks in a vertical active period of each frame and outputs the display gate signal and/or the sensing gate signal. The plurality of stages may be cascade-connected. An operation of an uppermost stage of the plurality of stages is activated in response to the gate start pulse, and an operation of each of remaining stages is activated in response to one of output signals (for examples, carry signals) of previous stages.

The gate shift register may be directly formed on a lower substrate of the display panel 10 in a gate-in panel (GIP) manner. The gate shift register may be formed in a non-display area (i.e., a bezel area) outside the pixel array of the display panel 10 through the same TFT process as the pixel array.

FIGS. 6 to 8 illustrate various examples of an external compensation module.

Referring to FIG. 6, the electroluminescent display according to the embodiment of the invention may include a driver IC (or referred to as “D-IC”) 20 mounted on a chip-on film (COF), a storage memory 50 and a power IC (or referred to as “P-IC”) 60 mounted on a flexible printed circuit board (FPCB), and a host system 40 mounted on a system printed circuit board (SPCB), in order to implement an external compensation module.

The driver IC (D-IC) 20 may further include a compensator 31 and a compensation memory 32 in addition to a timing controller 21, a sensor 22, and a data voltage generator 23. The external compensation module is implemented by forming the driver IC (D-IC) 20 and a compensation IC 30 (see FIG. 1) into one chip. The power IC (P-IC) 60 generates various driving powers required to operate the external compensation module.

Referring to FIG. 7, the electroluminescent display according to the embodiment of the invention may include a driver IC (or referred to as “D-IC”) 20 mounted on a chip-on film (COF), a storage memory 50 and a power IC (or referred to as “P-IC”) 60 mounted on a flexible printed circuit board (FPCB), and a host system 40 mounted on a system printed circuit board (SPCB), in order to implement an external compensation module.

The external compensation module of FIG. 7 is different from the external compensation module of FIG. 6 in that a compensator 31 and a compensation memory 32 are mounted on the host system 40 without being mounted on the driver IC 20. The external compensation module of FIG. 7 is implemented by integrating a compensation IC 30 (see FIG. 1) into the host system 40 and is meaningful in that the configuration of the driver IC 20 can be simplified.

Referring to FIG. 8, the electroluminescent display according to the embodiment of the invention may include a source driver IC SD-IC mounted on a chip-on film (COF), a storage memory 50, a compensation IC 30, a compensation memory 32, and a power IC (or referred to as “P-IC”) 60 mounted on a flexible printed circuit board (FPCB), and a host system 40 mounted on a system printed circuit board (SPCB), in order to implement an external compensation module.

The external compensation module of FIG. 8 is different from the external compensation modules of FIGS. 6 and 7 in that the configuration of the source driver IC SD-IC is further simplified by mounting only a data voltage generator 23 and a sensor 22 in the source driver IC SD-IC, and a timing controller 21 and the compensation memory 32 are mounted in the compensation IC 30 that is separately manufactured. The external compensation module of FIG. 8 can easily perform an uploading and downloading operation of a compensation parameter by together mounting the compensation IC 30, the storage memory 50, and the compensation memory 32 on the flexible printed circuit board.

FIGS. 9 and 10 illustrate an example of a pixel array included in the display panel.

Referring to FIGS. 9 and 10, a pixel array according to the embodiment of the invention includes a plurality of display lines L1, L2, L3 and L4 formed by adjacent pixels P. Each of the plurality of display lines L1, L2, L3 and L4 is not a physical signal line but a pixel block line formed by the adjacent pixels P. The horizontally adjacent pixels P on each of the display lines L1, L2, L3 and L4 are connected to the different data lines 140, respectively. The horizontally adjacent pixels P on each of the display lines L1, L2, L3 and L4 are connected to the different sensing lines 150 in units of M pixels, where M is a positive integer equal to or greater than 2. Hence, an aperture ratio of the display panel 10 can increase.

Referring to FIG. 9, the horizontally adjacent pixels P on each of the display lines L1, L2, L3 and L4 may be connected to a first gate line 160A and a second gate line 160B. In other words, two gate lines 160A and 160B may be allocated to each of the display lines L1, L2, L3 and L4 and each of the first gate line 160A and the second gate line 160B are coupled to only one of the display lines.

On the contrary, referring to FIG. 10, a first gate line 160A may be individually connected to the display lines L1, L2, L3 and L4, and a second gate line 160B may be shared by two adjacent display lines. In other words, the first and second display lines L1 and L2 may share one second gate line 160B, and the third and fourth display lines L3 and L3 may share another second gate line 160B. When the pixel array is designed to share some gate lines, an aperture ratio of the display panel 10 can increase. Further, the gate driver 15 can be simplified, and a bezel area, on which the gate driver 15 is mounted, can decrease.

FIG. 11 is an equivalent circuit diagram of a pixel included in a pixel array of FIGS. 9 and 10.

Referring to FIG. 11, each of pixels P constituting a pixel array may include an OLED, a driving TFT DT, a storage capacitor Cst, a first switching TFT ST1, and a second switching TFT ST2. However, the pixel configuration of FIG. 11 is merely an example, and embodiments are not limited thereto.

The pixel P of FIG. 11 may be a display target pixel and may be a sensing target pixel. Thus, a first gate signal SCAN1 may be a first display gate signal or a first sensing gate signal, and a second gate signal may be a second display gate signal or a second sensing gate signal. A data voltage supplied to the data line 140 by the data voltage generator 23 may be a display data voltage Vdata-DIS (see FIG. 1) or a sensing data voltage Vdata-SEN (see FIG. 1).

The OLED is a light emitting element that emits light with a pixel current input from the driving TFT DT. The OLED includes an anode electrode, a cathode electrode, and an organic compound layer between the anode electrode and the cathode electrode. The anode electrode is connected to a first node N1 via a storage capacitor Cst that is a gate electrode of the driving TFT DT. The cathode electrode is connected to an input terminal of a low potential driving voltage VSS. A gray level of an image displayed on a corresponding pixel P is determined depending on an amount of light emitted by the OLED.

The driving TFT DT is a driving element controlling a pixel current input to the OLED depending on a gate-to-source voltage Vgs of the driving TFT DT. The driving TFT DT includes a gate electrode connected to the first node N1, a drain electrode connected to an input terminal of a high potential driving voltage VDD, and a source electrode connected to a second node N2.

The storage capacitor Cst is connected between the first node N1 and the second node N2. The storage capacitor Cst holds the gate-to-source voltage Vgs of the driving TFT DT for a particular time.

The first switching TFT ST1 applies the data voltage on the data line 140 to the first node N1 in response to the first gate signal SCAN1. The first switching TFT ST1 includes a gate electrode connected to the first gate line 160A, a drain electrode connected to the data line 140, and a source electrode connected to the first node N1.

The second switching TFT ST2 switches on and off a current flow between the second node N2 and the sensing line 150 in response to the second gate signal SCAN2. The second switching TFT ST2 includes a gate electrode connected to the second gate line 160B, a drain electrode connected to the sensing line 150, and a source electrode connected to the second node N2. When the second switching TFT ST2 is turned on, the second node N2 and the sensor 22 are electrically connected.

FIG. 12 illustrates an exemplary configuration of a gate driver for driving the pixel array of FIG. 9.

Referring to FIG. 12, an exemplary configuration of the gate driver 15 according to the embodiment of the invention includes a first gate driver circuit 15A for generating a first gate signal SCAN1 to be supplied to the first gate lines 160A and a second gate driver circuit 15B for generating a second gate signal SCAN2 to be supplied to the second gate lines 160B.

More specifically, the gate driver 15 includes the first gate driver circuit 15A having as many stages SC1-STG1 to SC1-STGn as display lines L1 to Ln of the pixel array and the second gate driver circuit 15B having as many stages SC2-STG1 to SC2-STGn as the display lines L1 to Ln of the pixel array.

In FIG. 12, “SC1-DUM”, “SC2-DUM”, “SC1-MNT” and “SC2-MNT” denote dummy stages; “L Dummy” denotes a dummy display line; and “VGH” and “VGL” denote driving voltages applied to the stages. “VGH” is a gate high voltage, and “VGL” is a gate low voltage. The dummy stage and the dummy display line may be selectively included or excluded. Because a kickback effect of a display line adjacent to the dummy display line is reduced by the dummy stage and the dummy display line, a charging signal of the display line adjacent to the dummy display line can be stabilized. A pixel configuration of the dummy display line is similar to a pixel configuration of the display line, but may be configured not to emit light. Namely, the pixel of the dummy display line may not include an OLED or may not receive the data voltage or the gate signal.

The first gate driver circuit 15A generates a first display gate signal SCAN1 and sequentially supplies the first display gate signal SCAN1 to the first gate lines 160A positioned on the display target display lines (i.e., the first gate lines 160A connected to the display target pixels). Further, the first gate driver circuit 15A generates a first sensing gate signal SCAN1 and supplies the first sensing gate signal SCAN1 to the first gate line 160A positioned on at least one sensing target display line (i.e., the first gate line 160A connected to the sensing target pixels).

The stages SC1-STG1 to SC1-STGn constituting the first gate driver circuit 15A may be individually connected to the display lines, respectively. The stages SC1-STG1 to SC1-STGn of the first gate driver circuit 15A sequentially shift a first gate start pulse G1Vst in accordance with a first gate shift clock group including G1CLK1 to G1CLK4 and generate the first display gate signal SCAN1 and the first sensing gate signal SCAN1.

The second gate driver circuit 15B generates a second display gate signal SCAN2 and sequentially supplies the second display gate signal SCAN2 to the second gate lines 160B positioned on the display target display lines (i.e., the second gate lines 160B connected to the display target pixels). Further, the second gate driver circuit 15B generates a second sensing gate signal SCAN2 and supplies the second sensing gate signal SCAN2 to the second gate line 160B positioned on at least one sensing target display line (i.e., the second gate line 160B connected to the sensing target pixels).

The stages SC2-STG1 to SC2-STGn constituting the second gate driver circuit 15B may be individually connected to the display lines, respectively. The stages SC2-STG1 to SC2-STGn of the second gate driver circuit 15B sequentially shift a second gate start pulse G2Vst in accordance with a second gate shift clock group including G2CLK1 to G2CLK4 and generate the second display gate signal SCAN2 and the second sensing gate signal SCAN2.

FIG. 13 illustrates an exemplary configuration of a gate driver for driving the pixel array of FIG. 10.

Referring to FIG. 13, another exemplary configuration of the gate driver 15 according to the embodiment of the invention includes a first gate driver circuit 15A for generating a first gate signal SCAN1 to be supplied to the first gate lines 160A and a second gate driver circuit 15B for generating a second gate signal SCAN2 to be supplied to the second gate lines 160B.

More specifically, the gate driver 15 includes the first gate driver circuit 15A having as many stages SC1-STG1 to SC1-STGn as display lines L1 to Ln of the pixel array and the second gate driver circuit 15B having as many stages SC2-STG1 to SC2-STGn/2 as a half of the display lines L1 to Ln of the pixel array, where n is an even number.

The first gate driver circuit 15A generates a first display gate signal SCAN1 and sequentially supplies the first display gate signal SCAN1 to the first gate lines 160A positioned on the display target display lines (i.e., the first gate lines 160A connected to the display target pixels). Further, the first gate driver circuit 15A generates a first sensing gate signal SCAN1 and supplies the first sensing gate signal SCAN1 to the first gate line 160A positioned on at least one sensing target display line (i.e., the first gate line 160A connected to the sensing target pixels).

The stages SC1-STG1 to SC1-STGn constituting the first gate driver circuit 15A may be individually connected to the display lines, respectively. The stages SC1-STG1 to SC1-STGn of the first gate driver circuit 15A sequentially shift a first gate start pulse G1Vst in accordance with a first gate shift clock group including G1CLK1 to G1CLK4 and generate the first display gate signal SCAN1 and the first sensing gate signal SCAN1.

The second gate driver circuit 15B generates a second display gate signal SCAN2 and sequentially supplies the second display gate signal SCAN2 to the second gate lines 160B positioned on the display target display lines (i.e., the second gate lines 160B connected to the display target pixels). Further, the second gate driver circuit 15B generates a second sensing gate signal SCAN2 and supplies the second sensing gate signal SCAN2 to the second gate line 160B positioned on at least one sensing target display line (i.e., the second gate line 160B connected to the sensing target pixels).

Each of the stages SC2-STG1 to SC2-STGn/2 constituting the second gate driver circuit 15B may be commonly connected to the two display lines. The stages SC2-STG1 to SC2-STGn/2 of the second gate driver circuit 15B sequentially shift a second gate start pulse G2Vst in accordance with a second gate shift clock group including G2CLK1 to G2CLK4 and generate the second display gate signal SCAN2 and the second sensing gate signal SCAN2.

FIGS. 14 and 15 schematically illustrate an external compensation technique according to the embodiment of the invention in which a real-time sensing drive is performed in an extended vertical blanking interval.

The embodiment of the invention makes use of a vertical blanking interval VBP in accordance with a real-time external compensation method to sense electrical characteristics of the pixel P and extends the vertical blanking interval VBP in one frame, in order to secure a sufficient sensing time. Namely, the embodiment of the invention shortens a length of a vertical active period VAP in one frame and extends the vertical blanking interval VBP by the shortened length of the vertical active period VAP. Thus, an extended vertical blanking interval (during which sensing occurs) is longer than a normal vertical blanking interval (during which sensing does not occur), and a shortened vertical active period (which immediately precedes an extended vertical blanking interval) is shorter than a normal vertical active period (which immediately precedes a normal vertical blanking interval). In FIGS. 14 and 15, “S-VAP” denotes a shortened vertical active period, and “E-VBP” denotes an extended vertical blanking interval.

The timing controller 21 may compress a data timing control signal DDC and a gate timing control signal GDC allocated to the vertical active period VAP to shorten the vertical active period VAP. In embodiments disclosed herein, compressing the control signals DDC and GDC means reducing time required to write image data by decreasing a pulse width and/or a pulse cycle of the control signals DDC and GDC. The timing controller 21 may shorten the vertical active period VAP within a range that does not cause a problem in writing (charging) the image data. For example, when a frame frequency is 60 Hz, one frame is 16.67 ms. However, the timing controller 21 may shorten the vertical active period VAP to 8.33 ms.

The timing controller 21 allocates a remaining period excluding a shortened vertical active period S-VAP from one frame period as an extended vertical blanking interval E-VBP. Thus, a total time of a shortened vertical active period and an extended vertical blanking interval may equal a total time of a normal vertical active period and a normal vertical blanking interval.

The timing controller 21 outputs a first gate timing control signal for display-driving the plurality of display lines during the shortened vertical active period S-VAP and outputs a second gate timing control signal for sensing-driving some sensing target display lines of the plurality of display lines during the extended vertical blanking interval E-VBP.

The timing controller 21 may output the first gate timing control signal including a plurality of display gate shift clocks and may output a second gate timing control signal including at least one sensing gate shift clock, a plurality of pre-drive gate shift clocks, and a plurality of post-drive gate shift clocks.

Each extended vertical blanking interval may include one or more fast gate driving periods and one or more sensing periods. In embodiments disclosed herein, the sensing gate shift clock is applied during the sensing period to one stage of the gate driver 15 connected to a sensing target display line of the display panel 10 and is synchronized with the sensing gate signal. The pre-drive gate shift clock is output prior to the sensing gate shift clock during a fast gate driving period and is applied to other stages (i.e., first stages) of the gate driver 15 connected to some display lines of the display panel 10. The first stages are connected to a front end of the one stage. The first stages of the gate driver 15 generate first carry signals in synchronization with the pre-drive gate shift clock, and the one stage of the gate driver 15 connected to the sensing target display line is operated in response to a last signal of the first carry signals. The post-drive gate shift clock is output during another fast gate driving period following the sensing gate shift clock and is applied to other stages (i.e., second stages) of the gate driver 15 connected to remaining display lines of the display panel 10. The second stages are connected to a rear end of the one stage. The second stages of the gate driver 15 generate second carry signals in synchronization with the post-drive gate shift clock. Each of the second stages is operated in response to one of the second carry signals. In other words, the post-drive gate shift clock is needed to operate sequentially from a first stage in a vertical active period of a next frame. Considering such a series of operations, the some display lines may be positioned above the sensing target display line in the display panel 10, and the remaining display lines may be positioned below the sensing target display line in the display panel 10.

During the extended vertical blanking interval E-VBP, the timing controller 21 may set a cycle of the pre-drive gate shift clock and a cycle of the post-drive gate shift clock during the fast gate driving periods to be shorter than a cycle of the display gate shift clock of the shortened vertical active period S-VAP, thereby securing a time capable of widely setting a pulse width of the sensing gate shift clock relative to the pulse widths during the vertical active periods. An increase in the pulse width of the sensing gate shift clock means an increase in a sensing time. Thus, the accuracy of the sensing can be improved as the sensing time increases.

The embodiment of the invention performs the sensing drive operation in the extended vertical blanking interval E-VBP of each frame as shown in FIGS. 14 and 15. The embodiment of the invention obtains digital sensing data S-DATA through the sensing drive operation and updates a compensation value based on the digital sensing data S-DATA.

The embodiment of the invention senses at least one display line in the extended vertical blanking interval E-VBP of each frame. When the plurality of display lines is sensed in the extended vertical blanking interval E-VBP, the plurality of display lines may be sequentially sensed.

The pixels on the sensing target display line do not emit light. Thus, a position of the sensing target display line in each frame may be previously determined in a non-sequential manner (or randomly), in order to minimize or prevent the sensing target display line from being recognized as a line dim. For example, a position of the sensing target display line may be determined as a b-th display line in an Nth frame, may be determined as a c-th display line in a (n+1)th frame, and may be determined as an a-th display line in a (n+2)th frame. In embodiments disclosed herein, the c-th display line may be spatially spaced apart from the b-th display line by several to several hundreds of display lines and may be disposed below the b-th display line. Further, the a-th display line may be spatially spaced apart from the c-th display line by several to several hundreds of display lines and may be disposed on the c-th display line. However, embodiments are not limited thereto. The human eye responds more sensitively to sequential changes than non-sequential changes. Thus, when a position of the sensing target display line in each frame is determined in the non-sequential manner (or randomly), the sensing target display line can be minimized or prevented from being recognized as the line dim.

Because the embodiment of the invention performs the sensing drive operation in the extended vertical blanking interval E-VBP of each frame and reduces the cycle of the pre-drive gate shift clock and the cycle of the post-drive gate shift clock, the embodiment of the invention can easily perform the sensing drive on a desired display line without time constraints. More specifically, when a J-th display line of a display panel having a vertical resolution of N is sensed, where J is a positive integer less than N, a sensing drive of the J-th display line is performed after first to (J−1)th stages are operated. Because an operation of a J-th stage is activated in response to an output signal of the (J−1)th stage, the output signal of the (J−1)th stage is used as a carry signal in the sensing drive operation of the J-th display line. The embodiment of the invention can reduce a pre-time (required to operate the first to (J−1)th stages) before the sensing drive operation and a post-time (required to operate (J+1)th to Nth stages) after the sensing drive operation in the extended vertical blanking interval E-VBP by reducing the cycle of the pre-drive gate shift clock and the cycle of the post-drive gate shift clock. As a result, much time can be assigned to the sensing drive, and the accuracy of sensing can be improved.

FIGS. 16A to 16C illustrate operation examples of a gate driver in a vertical blanking interval extended corresponding to a display line, on which a real-time sensing drive operation is performed.

The timing controller 21 may output the pre-drive gate shift clock prior to the sensing gate shift clock and/or may output the post-drive gate shift clock following the sensing gate shift clock.

The timing controller 21 may output only the sensing gate shift clock and the post-drive gate shift clock, if necessary or desired. For example, as shown in FIG. 16A, when a first display line is sensed, the timing controller 21 may apply the sensing gate shift clock to a first stage of the gate driver and apply the post-drive gate shift clock to second to Nth stages of the gate driver.

The timing controller 21 may output all the pre-drive gate shift clock, the sensing gate shift clock, and the post-drive gate shift clock, if necessary or desired. For example, as shown in FIG. 16B, when a J-th display line is sensed, the timing controller 21 may apply the sensing gate shift clock to a j-th stage of the gate driver, apply the pre-drive gate shift clock to first to (J−1)th stages of the gate driver, and apply the post-drive gate shift clock to (J+1)th to Nth stages of the gate driver.

The timing controller 21 may output only the pre-drive gate shift clock and the sensing gate shift clock, if necessary or desired. For example, as shown in FIG. 16C, when an Nth display line is sensed, the timing controller 21 may apply the sensing gate shift clock to an Nth stage of the gate driver and apply the pre-drive gate shift clock to first to (N−1)th stages of the gate driver.

FIG. 17 illustrates an example of modifying a gate timing control signal to be input to a gate driver of FIG. 12 in order to secure a sensing time when a k-th display line is sensed in an extended vertical blanking interval. FIG. 18 illustrates an example of modifying a gate timing control signal to be input to a gate driver of FIG. 13 in order to secure a sensing time when a k-th display line is sensed in an extended vertical blanking interval.

Referring to FIGS. 17 and 18, the embodiment of the invention modifies gate shift clocks G1CLK1 to G1CLK4 and G2CLK1 to G2CLK4 to be input to the gate driver 15, in order to secure a more sufficient sensing time in an extended vertical blanking interval E-VBP.

To this end, the timing controller 21 causes cycles of a pre-drive gate shift clock B and a post-drive gate shift clock D to be input to the gate driver 15 during an extended vertical blanking interval E-VBP to be shorter than a cycle of a display gate shift clock A to be input to the gate driver 15 during a shortened vertical active period S-VAP.

The timing controller 21 may decrease pulse widths of the pre-drive gate shift clock B during a first fast gate driving period and the post-drive gate shift clock D during a second fast gate driving period while decreasing the cycles of the pre-drive gate shift clock B and the post-drive gate shift clock D. The pre-drive gate shift clock B and the post-drive gate shift clock D are signals that are interlocked with a carry signal and are irrelevant to a supply timing of the data voltage. Namely, while the pre-drive gate shift clock B and the post-drive gate shift clock D are applied to the gate driver 15, no data voltage is applied to the display panel 10. Because a data enable signal is not toggled during the input of the pre-drive gate shift clock B and the post-drive gate shift clock D, the data voltage generator 23 stops an output of the data voltage in synchronization with the pre-drive gate shift clock B and the post-drive gate shift clock D. Thus, the cycles and the pulse widths of the pre-drive gate shift clock B and the post-drive gate shift clock D can decrease without considering a charging time of the data voltage.

The timing controller 21 allocates a sufficient time, that is obtained by compressing the pre-drive gate shift clock B and the post-drive gate shift clock D in the extended vertical blanking interval E-VBP, to a sensing gate shift clock C during the sensing period.

Assuming that a k-th display line is sensed in the extended vertical blanking interval E-VBP, first to (k−1)th stages of the gate driver 15 are driven rapidly in response to the pre-drive gate shift clock B, and then a kth stage of the gate driver 15 is driven in response to the sensing gate shift clock C. Subsequently, (k+1)th to nth stages of the gate driver 15 are driven rapidly in response to the post-drive gate shift clock D.

On the other hand, in the shortened vertical active period S-VAP, the first to n-th stages of the gate driver 15 are driven in response to a display gate shift clock A relatively slower than the remaining stages, other than the k-th stage, that are operated in the extended vertical blanking interval E-VBP.

The timing controller 21 may output sensing gate shift clocks G1CLK1 and G2CLK1 each including a first pulse (P1/P1′) (e.g., an initialization gate pulse) and a second pulse (P2/P2′) (e.g., a sensing gate pulse), that are successively arranged, in the extended vertical blanking interval E-VBP. In embodiments disclosed herein, the sensing gate shift clocks G1CLK1 and G2CLK1 are k-th clocks applied to the k-th stage. The first pulses (P1/P1′) of the sensing gate shift clocks G1CLK1 and G2CLK1 are synchronized with a supply timing of a reset data voltage Vdata-BLK, and the second pulses (P2/P2′) of the sensing gate shift clocks G1CLK1 and G2CLK1 are synchronized with a supply timing of a sensing data voltage Vdata-SEN. The reset data voltage Vdata-BLK may be a voltage of a particular gray level such as a black gray data voltage.

The data voltage generator 23 may apply the reset data voltage Vdata-BLK to the pixels on the sensing target display line of the display panel 10 in synchronization with the sensing gate shift clocks G1CLK1 and G2CLK1 of the first pulse (P1/P1′), thereby initializing the pixels to a predefined voltage. When the pixels are initialized with the reset data voltage Vdata-BLK, a gate potential of the driving element is uniformly held at a black gray level.

Subsequently, the data voltage generator 23 may apply the sensing data voltage Vdata-SEN to the pixels on the sensing target display line of the display panel 10 in synchronization with the sensing gate shift clocks G1CLK1 and G2CLK1 of the second pulse (P2/P2′). When the sensing data voltage Vdata-SEN is applied to the pixels in a state the pixels are initialized at the black gray level, the gate potential of the driving element may be accurately set to the sensing data voltage Vdata-SEN. A sensing time may be determined as a high level period of the second pulse P2′. In other words, the sensing drive is performed in response to a sampling signal SEN in the high level period of the second pulse P2′, and the ADC outputs a sensing result as digital sensing data. FIGS. 17 and 18 illustrate that the first pulse (P1/P1′) used to apply the reset data voltage Vdata-BLK to the pixel is arranged prior to the sensing time. However, the embodiments are not limited thereto. For example, the first pulse (P1/P1′) may be arranged after the sensing time.

As described above, the embodiments of the invention can easily perform the sensing drive on a desired display line without time constraints by extending the vertical blanking interval and performing sensing drive in the extended vertical blanking interval.

Further, the embodiments of the invention can secure a sufficient sensing time and improve the accuracy of the sensing by further decreasing a clock cycle of the gate timing control signal in the vertical blanking interval than the vertical active period.

Although the embodiments have been described with reference to a number of illustrative embodiments thereof, numerous other modifications and embodiments may be devised by those skilled in the art that will fall within the scope of the principles of this disclosure. In particular, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art. 

What is claimed is:
 1. A display device comprising: a display panel including a plurality of pixels arranged in display lines, a plurality of gate lines, and a plurality of data lines, the display lines driven with the data signals from the data lines according to timing of gate pulses from the gate lines to display image data during vertical active periods; and a timing controller to supply gate timing signals to a gate driver as a sequence of clock pulses that sequentially select different ones of the display lines for receiving the data signals during the vertical active periods and for selecting a sensing target display line for receiving a sensing signal during vertical blanking intervals in between the vertical active periods, the clock pulses having a first clock cycle during the vertical active periods and the clock pulses having a second clock cycle during at least a portion of the vertical blanking intervals, the second clock cycle shorter than the first clock cycle, wherein each vertical blanking interval includes at least one fast gate driving period and a sensing period, wherein the sensing target display line is sensed during the sensing period, wherein the timing controller is configured to supply the clock pulses to the gate driver to cause the gate driver to sequentially select a subset of the display lines prior to or following the sensing target display line during the at least one fast gate driving period, and wherein electrical characteristics of the sensing target display line are sensed in the sensing period prior to or following the at least one fast gate driving period.
 2. The display device of claim 1, wherein electrical characteristics of the sensing target display line are sensed during the sensing period, and wherein the timing controller supplies the clock pulses according to the second clock cycle during the at least one fast gate driving period.
 3. The display device of claim 2, wherein the timing controller provides a sensing clock pulse to the gate driver during the sensing period to cause the gate driver to select the sensing target display line, a pulse width of the sensing clock pulse wider than a pulse width of the clock pulses during the vertical active periods.
 4. The display device of claim 3, wherein the timing controller provides an initialization clock pulse to the gate driver during the sensing period to cause the gate driver to select the sensing target display line, and a data driver applies an initialization data voltage to the sensing target display line during the initialization clock pulse.
 5. The display device of claim 1, wherein the gate driver supplies first gate pulses to first gate lines of the plurality of gate lines and supplies second gate pulses to second gate lines of the plurality of gate lines, and wherein each of the first gate lines and each of the second gate lines are coupled to only one of the display lines.
 6. The display device of claim 1, wherein the gate driver supplies first gate pulses to first gate lines of the plurality of gate lines and supplies second gate pulses to second gate lines of the plurality of gate lines, and wherein each of the first gate lines are coupled to only one of the display lines, and wherein each of the second gate lines are coupled to at least two display lines.
 7. The display device of claim 6, wherein the first gate pulses on the first gate lines have a different width than the second gate pulses on the second gate lines.
 8. The display device of claim 1, further comprising: a sensing circuit to receive electrical characteristics of the sensing target display lines during the vertical blanking intervals; and a compensator circuit to compensate for differences in the sensed electrical characteristics.
 9. The display device of claim 1, wherein a pulse width of a sensing clock pulse in the sensing period is wider than a pulse width of a gate clock pulse in the at least one fast gate driving period.
 10. A display device comprising: a display panel including a plurality of pixels arranged in display lines, a plurality of gate lines including display gate lines, and a plurality of data lines, the display lines driven with data signals from the data lines according to timing of gate pulses from the display gate lines to display image data during vertical active periods, wherein vertical blanking intervals occur in in alternating order with the vertical active periods; and a timing controller to supply timing signals to a gate driver as a sequence of clock pulses to cause the gate driver to sequentially select different ones of the display lines for receiving the data signals during the vertical active periods and to select a sensing target display line for sensing of electrical characteristics during the vertical blanking intervals, wherein the clock pulses have a first clock cycle during the vertical active periods and the clock pulses having a second clock cycle during at least a portion of the vertical blanking intervals, the second clock cycle shorter than the first clock cycle, wherein each vertical blanking interval includes at least one fast gate driving period and a sensing period, wherein the sensing target display line is sensed during the sensing period, wherein the timing controller is configured to supply the clock pulses to the gate driver to cause the gate driver to sequentially select a subset of the display lines prior to or following the sensing target display line during the at least one fast gate driving period, and wherein electrical characteristics of the sensing target display line are sensed in the sensing period prior to or following the at least one fast gate driving period.
 11. The display device of claim 10, wherein each of the vertical blanking intervals occurs immediately adjacent to one of the vertical active periods.
 12. The display device of claim 10, wherein a total time of one of the vertical blanking intervals equals a total time of one of the vertical active periods.
 13. The display device of claim 10, wherein electrical characteristics of the sensing target display line of the display panel are sensed during the sensing period, and wherein the timing controller supplies the clock pulses according to the second clock cycle during the at least one fast gate driving period.
 14. The display device of claim 10, further comprising: a sensing circuit to receive the electrical characteristics of the sensing target display lines during the vertical blanking intervals; and a compensator circuit to compensate for differences in the sensed electrical characteristics.
 15. The display device of claim 10, wherein a pulse width of a sensing clock pulse in the sensing period is wider than a pulse width of a gate clock pulse in the at least one fast gate driving period.
 16. A controller for a display panel having a plurality of pixels arranged in display lines, a plurality of gate lines including display gate lines, and a plurality of data lines, the controller comprising: a timing controller to control timing of vertical active periods and vertical blanking intervals in between the vertical active periods, wherein during the vertical active periods, the timing controller supplies first gate timing signals to a gate driver as a first sequence of clock pulses that causes the gate driver to sequentially provide first gate pulses on the plurality of display gate lines to select different display lines for receiving data signals to display image data, and wherein during the vertical blanking intervals, the timing controller supplies second gate timing signals to the gate driver as a second sequence of clock pulses that causes the gate driver to select a sensing target display line for sensing, and wherein first gate timing signals during the vertical active periods have a first clock cycle and second gate timing signals during at least a portion of the vertical blanking intervals have a second clock cycle, the second clock cycle shorter than the first clock cycle; and a sensing circuit to receive electrical characteristics of the sensing target display lines during the vertical blanking intervals, wherein each vertical blanking interval includes at least one fast gate driving period and a sensing period, wherein the sensing target display line is sensed during the sensing period, wherein the timing controller is configured to supply the clock pulses to the gate driver to cause the gate driver to sequentially select a subset of the display lines prior to or following the sensing target display line during the at least one fast gate driving period, and wherein electrical characteristics of the sensing target display line are sensed in the sensing period prior to or following the at least one fast gate driving period.
 17. The controller of claim 16, wherein the electrical characteristics of a sensing target display line are sensed during the sensing period, and wherein the timing controller supplies the second clock pulses according to the second clock cycle during the at least one fast gate driving period.
 18. The controller of claim 17, wherein the timing controller provides a sensing clock pulse to the gate driver during the sensing period to cause the gate driver to select the sensing target display line, a pulse width of the sensing clock pulse wider than a pulse width of the clock pulses during the vertical active periods.
 19. The controller of claim 18, wherein the timing controller provides an initialization clock pulse to the gate driver during the sensing period to cause the gate driver to select the sensing target display line, and a data driver applies an initialization data voltage to the sensing target display line during the initialization clock pulse.
 20. The controller of claim 16, wherein a pulse width of a sensing clock pulse in the sensing period is wider than a pulse width of a gate clock pulse in the at least one fast gate driving period. 